1. Field of Invention
The present invention relates a CMOS circuit, more specifically, a CMOS leakage current control circuit with a single low-voltage power supply.
2. Related Art
The control of leakage current is very important in the design of IC (Integrated Circuit), especially in the design of low-power and low-voltage IC.
FIG. 1 illustrates a prior art leakage current control circuit, namely, a super cut-off CMOS (SCCMOS), having an active mode and a sleep mode. The active mode means that the core circuit is in an operating state. After receiving an external sleep mode control signal (SLP), the core circuit will stop operation and shift into an idle status (i.e., a sleep mode) to lower power consumption. As shown in the drawing, the prior art leakage current control circuit includes a high-voltage generating circuit 102, a switch circuit, for example a power transistor, 104, a sleep-control circuit 106, a plurality of flip-flops 110, 113 and 116, and a plurality of combinational circuits 112 and 115. Each of the flip-flops 110, 113 and 116 has a corresponding memory device 111, 114 and 117, respectively, which back up the data in the flip-flops 110, 113 and 116 when the circuit is in a sleep mode. The operation of the control circuit will be detailed below.
A first end of the transistor 104 is connected to a first power supply line VDD, and a second end of the transistor is connected to a second power supply line VDDV, and the gate electrode of the transistor 104 is connected to the output of the high-voltage generating circuit 102. In response to an internal sleep signal (SLPI), the high-voltage generating circuit 102 generates and supplies a high-voltage VGP higher than the supply voltage VDD to the gate electrode of the transistor 104. This is called the super cutoff mechanism. The flip-flops 110, 113, and 116 are connected between the second power supply line VDDV and the first ground line GND. The memory devices 111, 114 and 117 are connected between the first power supply line VDD and the second ground line VSS. The combinational circuits 112 and 115 are connected between the second power supply line VDDV and the first ground line GND. The control circuit 106 is connected to the first power supply line VDD and the second power supply line VDDV. After the control circuit 106 receives an external sleep mode control signal SLP, it outputs a corresponding internal sleep mode signal SLPI. It also outputs an internal clock signal CK to the flip-flops 110, 113 and 116 in response to an external clock signal CKE. Meanwhile, the wordline signal WL controls the operation of the memory device 111, 114, and 117.
The circuit shown in the FIG. 1 applies the super cutoff mechanism to the power transistor 104 to limit the leakage current in the sleep mode to an average of pico-ampere each gate. By applying the super cutoff scheme, the supply voltage VDD can also be reduced to a very low voltage, say 0.5V. However, because each of the flip-flops has an extra memory device for data backup in the sleep mode, and because the memory devices are high threshold-voltage elements that cannot operate under low-voltage, an extra voltage of −0.5V (VSS) besides a power supply of 0.5V (VDD) has to be provided to activate the memory devices. Further, the wakeup time of the entire circuit from the sleep mode to the active mode is long.
In order to solve the problems described above, the prior art provides another circuit, as shown in FIG. 2, an zigzag super cut-off CMOS (ZSCCMOS), including a high-voltage generating circuit 201, a low-voltage generating circuit 202, a first switch circuit, for example a P-channel power transistor, 203, a second switch circuit, for example an N-channel power transistor, 204, a control circuit 206, a plurality of flip-flops 210 and 218, and a plurality of combinational circuits 212, 214, and 216. The flip-flops 210 and 218 have different properties. The operation of the circuit is detailed below.
A first end of the first P-channel power transistor 203 is connected to a first power supply line VDD, a second end of the power transistor 203 is connected to a second power supply line VDDV, and the gate electrode of the power transistor 203 receives the output of a high-voltage generating circuit 201. A first end of the second N-channel power transistor 204 is connected to the first ground line GND, a second end of the power transistor 204 is connected to a second ground line GNDV, and the gate electrode of the power transistor 204 receives the output of a low-voltage generating circuit 202. In response to an internal sleep mode signal SLPI, the high-voltage generating circuit 201 generates an output voltage VGP higher than the power supply voltage VDD and supplies the output voltage VGP to the gate electrode of the first transistor 203. In response to an internal sleep mode signal SLPI#, the low-voltage generating circuit 202 generates an output voltage VGN lower than the voltage GND and supplies the sleep signal SLPI# to the gate electrode of the second transistor 204. The flip-flops 210 and 218 must be connected to VDD, VDDV, VGP, GND, GNDV, and VGN. The combinational circuits 212 and 216 are connected between the second power supply line VDDV and the first ground line GND. The combinational circuit 214 is connected between the first power supply line VDD and the second ground line GNDV. The control circuit 206 generates internal sleep mode signals SPLI and SLPI# in response to an external sleep mode signal SLP. It also outputs an internal clock signal CK in response to an external clock signal CKE to the flip-flops 210 and 218. In the sleep mode, the input of the combinational circuit 212 is maintained at a high level and the output of the combinational circuit 212 is maintained at a low level, the input of the combinational circuit 214 is maintained at a low level and the output of the combinational circuit 214 is maintained at a high level, the input of the combinational circuit 216 is maintained at a high level and the output of the combinational 216 is maintained at a low level.
The circuit shown in FIG. 2 may reduce the wakeup time. However, because each pipeline stage needs a special flip-flop (flip-flop 210) as an input phase-locking circuit and an ordinary flip-flop (flip-flop 218) as an output terminal to save data when in the sleep mode, each pipeline stage of the circuit includes two kinds of flip-flops. This means the circuit may not be used in a typical consecutive pipeline system or the circuit shown in FIG. 2 can only be used at a specific pipeline stage. Although ZSCCMOS is single low-voltage circuit, its flip-flops use more wires to control the operation in the sleep mode. Therefore, more wire resources are needed.